1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and particularly, to a semiconductor integrated circuit device that has a ROM decoder for converting an n-bit data signal (n represents an integer of 2 or more) representing a gradation level (the n-bit data signal corresponding to a digital signal supplied as image data) to a gradation voltage having the corresponding level of the n-th power of 2 gradation (the gradation voltage corresponding to an analog signal), and drives data lines of a liquid crystal panel on the basis of the gradation voltage thus achieved.
Further, the present invention relates to driving a liquid crystal display device using the semiconductor integrated circuit device.
2. Description of the Related Art
Liquid crystal display devices have been applied to various types of devices such as a personal computer, etc. from the viewpoint of such an advantage that they can be designed to have thin and light bodies and the power consumption thereof is low. Particularly, active matrix type color liquid crystal display devices that are advantageous to control image quality with high precision have been most prevailingly used.
As shown in FIG. 1, a liquid crystal display module of such a type of liquid crystal display device is equipped with liquid crystal display (LCD) panel 101 , control circuit (hereinafter referred to as “controller”) 102 comprising a semiconductor integrated circuit device (hereinafter referred to as “IC”), plural scan-side driving circuits (hereinafter referred to as “scan-side drivers”) 103 and data-side driving circuits (hereinafter referred to as “data-side drivers”) 104 which are formed of ICs. The liquid crystal panel 101 is designed in a structure having a semiconductor substrate on which transparent pixel electrodes and thin film transistors (TFT) are arranged, a opposite substrate having a single transparent electrode on the whole surface thereof, and liquid crystal which is sealingly filled in the gap between these two substrates arranged so as to face each other. A predetermined voltage (hereinafter referred to as “common voltage Vcom”) is applied to the opposite substrate electrode, and a predetermined voltage is applied to each pixel electrode by controlling TFT having a switching function, whereby the transmissivity of liquid crystal is varied by the potential difference between each pixel electrode and the opposite substrate electrode to display an image. Here, a variable voltage (hereinafter referred to as “gradation voltage”) is applied to each pixel electrode to perform an intermediate gradation (gradation display) of an image.
Data lines for transmitting gradation voltages to be applied to the respective pixel electrodes and scan lines for transmitting a switching control signal (scan signal) for TFTs are wired on the semiconductor substrate.
The input side of the controller 102 is connected to personal computer (PC) 105, and the output side thereof is connected to the scan-side drivers 103 and the data-side drivers 104. The output sides of the scan-side drivers 103 and data-side drivers 104 are connected to the scan lines and data lines of the liquid crystal panel 101, respectively. The scan-side drivers 103 and data-side drivers 104 are restricted in chip size by restriction on the manufacture thereof. Accordingly, the output numbers corresponding to the scan lines and data lines which can be output by one IC is limited, and thus it is necessary to arrange plural ICs on the outer periphery of the liquid crystal panel 101 when the size of the liquid crystal panel 101 is large. For example, in the case of a liquid crystal panel for color display of 1024×768 pixels, the respective drivers 103, 104 are practically mounted in a module under the following restriction.    (1) The scan-side drivers 103 need to drive 768 driving lines. Therefore, when each scan-side driver 103 has a driving capability for 192 driving lines, totally four scan-side drivers 103 are needed, and they are arranged in cascade-connection at one side (left side) on the outer periphery of the liquid crystal panel 101.    (2) The data-side drivers 104 need to drive data lines of 1024×3=3072 because three data lines of R(red), G(green), B(blue) are needed for color display of one pixel. For example when each data-side driver 104 has a driving capability of 384 data lines, totally eight data-side drivers 104 are needed and they are arranged in cascade-connection at one side (upper side) on the outer periphery of the liquid crystal panel 101.
A power supply circuit (not shown) for supplying a common voltage Vcom is connected to the opposite substrate electrode.
Image data are transmitted from PC 105 to the controller 102 of the liquid crystal display module, and clock signals, etc. are transmitted from the controller 102 to the respective scan-side drivers 103 in parallel. A vertical synchronization start signal STV is transmitted to the scan-side driver 103 at the first stage, and transferred to each of the cascade-connected scan-side drivers 103 at the subsequent stages one after another.
Timing signals such as clock signals, etc. and data signals are transmitted from the controller 102 to the data-side drivers 104 in parallel. A horizontal synchronization start signal STH is transmitted to the data-side driver 104 at the first stage, and transferred to each of the cascade-connected data-side drivers 104 at the subsequent stages one after another.
Pulse-shaped scan signals are transmitted from the scan-side drivers 103 to the respective scan lines. When the scan signal applied to a scan line is set to high level, all the TFTs connected to the scan line are turned on, and gradation voltages transmitted to the data lines from the data-side drivers 104 are applied to the pixel electrodes through the turn-on TFTs. At this time, the common voltage Vcom is applied from the power supply circuit (not shown) to the opposite substrate electrode. When the scan signal is set to low level and the TFTs are turned off, the potential difference between the pixel electrode and the opposite substrate electrode is kept until a next gradation voltage is applied to the pixel electrode. By transmitting the scan signal to each scan line one after another, predetermined gradation voltages are applied to all the pixel electrodes, and the gradation voltages are rewritten at a frame period, whereby an image can be displayed.
As the data-side driver 104 described above is known a driver equipped with an ROM decoder for converting a digital signal representing an input gradation level to a gradation voltage of an analog signal due to output the graduation voltage (for example, see JPA-2000-221927). A data-side driver using a dot reverse driving method disclosed in JP-A-2000-221927 will be described with reference to FIGS. 2 to 4 on the assumption that the number of data lines is S and the data-side driver has a driving capability of 384.
First, the construction of the data-side driver will be described with reference to FIG. 2.
In FIG. 2, in the data-side driver 120, by supplying a data signal DATA of 6 bits for each color of R, G, B as image data, one gradation voltage VPx, VNx corresponding to the logic of the data signal DATA out of positive-polarity and negative-polarity gradation voltages VP1 to VP64, VN1 to VN64 which are the 6th power of 2 (=64) gradation is alternately applied to each of the 384 data lines every horizontal period while the polarity is alternately changed between the odd-numbered lined and the even-numbered lines.
The data-side driver 120 is equipped with shift register 121, data register 122, data latch 123, level shifter 124, digital analog conversion circuit (hereinafter referred to as “DA converter”) 125 and voltage follower output circuit 126 as main circuits as shown in FIG. 2.
The shift register 121 is designed to have 64-bit interactivity, for example. In this shift register 121, for example, a right shift start pulse input/output STHR is selected on the basis of a shift direction switching signal R/L, the “H” level of the start pulse STHR is read in on the basis of the edge of a clock signal CLK every horizontal period, and control signals C1, C2, . . . , C64 for data reading are generated one after another and supplied to the data register 122.
The data register 122 reads the data signal DATA of one scan line supplied at a width of 36 bits (6-bit×6-bit (RGB×2)) on the basis of the control signals C1, C2, . . . , C64 of the shift register 121 every horizontal period.
The data latch 123 holds the data signal DATA of one scan line read into the data register 122 at the timing of a strobe signal STB every horizontal period, and also collectively supplies the data signal DATA thus held to the level shifter 124.
The level shifter 124 increases the voltage level of the data signal DATA from the data latch 123 every horizontal period, and then supplies the data signal to the DA converter 125.
The DA converter 125 sets the data signal thus supplied so that the polarity is alternately changed between the odd-numbered output and the even-numbered output every horizontal period, and supplies, in conformity with each output thereof, one gradation voltage corresponding to the data signal DATA out of the gradation voltages of 64 gradations generated in a gradation voltage generating circuit contained in the DA converter to the voltage follower output circuit 126.
The voltage follower output circuit 126 outputs the gradation voltage thus supplied to each of the 384 data lines with enhanced driving capability every horizontal period while the polarity is alternately changed between the odd-numbered lines and the even-numbered lines.
Next, the construction of the data-side driver 120 on the semiconductor chip will be described with reference to FIG. 3.
In FIG. 3, semiconductor chip 201 is an elongated rectangular semiconductor chip, and internal circuit 202 is disposed at the center portion along the long side in the semiconductor chip 201. As not shown, the output pads corresponding to the data lines of 384 are connected to the internal circuit 202 and disposed at the outer peripheral portion which faces the liquid crystal panel out of both of the outer peripheral portions of the internal circuit 202 in the longitudinal direction, and input pads for start pulse input/output, shift direction switching input, clock input, data input, latch input, etc. and power supply pads for positive power supply, negative power supply and γ-correction power supply are connected to the internal circuit 202 and disposed at the other outer peripheral portion of the internal circuit 202. Some of the output pads may be disposed at a short-side portion or a long-side portion at the input side other than at the long-side portion facing the liquid crystal panel. From the viewpoint of layout, the inside of the internal circuit 202 is designed so that circuit blocks 203 each having L=6 outputs at M=S/L=64 stages are arranged so as to be adjacent to one another in the longitudinal direction of the chip and totally S=384 outputs are achieved. With respect to the circuit blocks 203, the circuit arrangement is partially different between the circuit block 203a at the odd-numbered stage and the circuit block 203b at the even-numbered stage.
Next, the circuit blocks 203a and 203b will be described with reference to FIG. 4. The gradation voltage generating circuit contained in the DA converter and the power supply input and signal input from the external are omitted from the illustration.
Both of the circuit blocks 203a, 203b comprise one-stage shift register 211, data registers 212 of six stages, first change-over switches 213 of three stages, latches 214 of six stages, level shifters 215 of six stages, DA converter 216, second change-over switches 217 of three stages and voltage follower output circuits 218 of six stages. These circuits 211 to 218 described above are successively arranged in the stage structure so that six outputs S1 to S6 are arranged at the long-side side of the liquid crystal panel side of the semiconductor chip 201.
The one-stage shift register 211 generates a control signal for data reading by reading the H level of the start pulse on the basis of the edge of the clock input. The one-stage shift register 211 corresponds to six outputs S1 to S6.
The data registers 212 of six stages read display data of 6 bits as n bits on the basis of the control signal from the shift register 211. Each of the first change-over switches 213 of three stages has two inputs and two outputs to alternately output the display data picked up at an i-th stage (odd-numbered stage) (i=1, 3, 5) of the data registers 212 and an (i+1)-th stage (even-numbered stage) of the data registers 212.
The latches 214 of six stages hold and collectively output the display data from the first change-over switches 213 at the timing of the strobe signal STB. Each of level shifters 215 of six stages converts the voltage level of the display data from the corresponding latch 214 to a level at which the next stage circuit can be driven
The DA converter 216 includes P-channel type ROM decoders (hereinafter referred to as “P-ROM decoders”) 216P of three stages and N-channel type ROM decoders (hereinafter referred to as “N-ROM decoders”) 216N of three stages. The P-channel type ROM decoders 216P of three stages are supplied with positive gradation voltages of 64 gradations to output the gradation voltages from the respective stages one by one on the basis of the display data from the corresponding level shifters 215 and are collectively arranged in a cluster so as to be adjacent to one another in the longitudinal direction of the chip. The N-channel type ROM decoders 216N of three stages are supplied with negative gradation voltages of 64 gradations to output the gradation voltages from the respective stages one by one on the basis of the display data from the corresponding level shifters 215 and are collectively arranged in a cluster so as to be adjacent to one another in the longitudinal direction of the chip. The P-ROM decoders and N-ROM decoders are arranged so as to be adjacent to one another in the longitudinal direction of the semiconductor chip 201.
Each of the second change-over switches 217 of three stages has two inputs and two outputs to alternately output the positive and negative gradation voltages from the DA converter 216 to each of one output side and the other output side. Each of the voltage follower output circuits 218 of six stages outputs the gradation voltages from the one output side and the other output side of the corresponding second change-over switch 217 to an odd-numbered stage and an even-numbered stage respectively.
The shift register 211 are connected to the data registers 212 through wires 221, the data registers 212 are connected to the first change-over switches 213 through wires 222, the first change-over switches 213 are connected to the latches 214 through wires 223, the latches 214 are connected to the level shifters 215 through wires 224, the level shifters 215 are connected to the DA converter 216 through wires 225, the DA converter 216 is connected to the second change-over switches 217 through wires 226 and the second change-over switches 217 are connected to the voltage follower output circuits 218 through wires 227.
It has been also required to further reduce the lay-out area and gate capacity of the ROM decoders 216N, 216P on the semiconductor chip in the data-side driver 120 described above.